1. Field of the Invention
This invention relates to a thin film transistor (TFT) matrix substrate having TFTs arranged in a matrix pattern, and more particularly to a TFT matrix substrate having a testing circuit for testing the TFT matrix.
2. Description of the Related Art
Generally, a TFT matrix substrate has TFTs formed in a rectangular shape and includes data lines and gate lines. Each data line connects drain electrodes of the TFTs and each gate line connects gate electrodes of the TFTs to each other. Each of the TFTs connected between the gate lines and the data lines responds to a scanning signal from the gate line to switch a data signal to be applied to a pixel cell, such as a liquid crystal cell. The gate lines for applying the scanning signal to the TFTs and the data lines for applying the data signal may get disconnected or break due to a manufacturing tolerance of the TFT matrix substrate, a working error, and so on. If the gate line is broken or disconnected, then the TFTs connected to the gate line can not be driven. On the other hand, if the data line is broken or disconnected, then a data signal is not applied to a part of TFTs. In order to check if the gate line or the data line has a break, the TFT matrix substrate is provided with a testing circuit.
For example, as shown in FIG. 1, a TFT matrix substrate having a testing circuit includes TFTs 14 arranged in each intersection between the gate line 10 and the data line 12. The TFTs 14 apply respectively voltage signals on the data lines 12 to pixel electrodes 14A when a high level voltage is supplied to the gate lines 10. Odd-numbered gate lines of the gate lines 10 are commonly connected to a first test line 16A while the remaining even-numbered gate lines of the gate lines 10 are commonly connected to a second test line 16B. Odd-numbered data lines of the data lines 12 are commonly connected to a third test line 16C while the remaining even-numbered data lines of the data lines 12 are commonly connected to a fourth test line 16D. Each end of the first and second test lines 16A and 16B is provided with gate test pads 18A for receiving a gate test signal. The first and second test lines 16A and 16B apply the gate test signal from the gate test pads 18A to the gate lines 10 when it is intended to test if any gate lines 10 are broken down. Likewise, each end of the third and fourth test lines 16C and 16D is provided with data test pads 18B for receiving a data test signal. The third and fourth test lines 16C and 16D apply the data test signal from the data test pads 18B to the data lines 12 when it is intended to test if any data lines 12 have a break therein.
Further, the TFT matrix substrate includes static electricity preventing circuits or static electricity preventing patterns or devices 20 connected to each of the gate lines 10 and the data lines 12. The static electricity preventing patterns 20 connected to the gate lines 10 are positioned at the opposite sides to the first and second test lines 16A and 16B and, at the same time, commonly connected to a low level gate line 22. The static electricity preventing patterns 20 connected to the data lines 12 are positioned at the opposite sides to the third and fourth test lines 16C and 16D and, at the same time, commonly connected to a common voltage line 24. Such static electricity preventing patterns 20 intercept static electricity to be transferred to the gate lines 10 or the data lines 12, thereby protecting the TFTs 14 from the static electricity.
In the TFT matrix substrate as described above, there occurs a case where the break in the gate line 10 is not detected because of current leaks due to the static electricity preventing circuits or static electricity preventing patterns. More specifically, the static electricity preventing pattern 20 connected to the broken gate line 10 or the broken data line 12 forces a test signal voltage to be charged into the low level gate voltage line 22 or the common voltage line 24, upon testing of the substrate. Then, the voltage charged in the low level gate voltage line 22 or the common voltage line 24 is applied to the broken gate line 10 or the broken data line 12. As a result, the broken gate line 10 or the broken data line 24 can be normally driven. Due to this, the break in the gate line 10 and data lines 12 is not readily detected.